The present invention relates generally to non-volatile memory devices and, more particularly, to a timing system and method for embedded and test modes within flash electrically erasable programmable read-only memory (EEPROM) devices.
A flash memory is a storage device that is capable of retaining stored information in the absence of continuous power. The information is stored in a plurality of flash transistors that are electrically connected and formed on a silicone substrate. A flash transistor is typically referred to as a memory cell and includes a source, a drain, a floating gate and a control gate. Flash memory are formed by rows and columns of memory cells that form a memory array. The memory array is typically a matrix where the control gates of the memory cells in a row are electrically connected to form a respective wordline and the drains of the memory cells in a column are electrically connected to form a respective bitline. Generally, the sources of the memory cells are electrically connected to form a common source line.
To perform a read, program or erase of memory cells in the memory array, a respective predetermined voltage is applied to the wordlines, bitlines and source lines of the memory cells. In addition to the read, program and erase, other typical operations performed on the memory cells are a program verify and an erase verify. The program verify ensures that the memory cells have been properly programmed and the erase verify ensures that the memory cells have been properly erased. If memory cells are not properly programmed or erased, corrective actions are taken by the flash memory to achieve the desired programmed or erased state.
The process of reading, programming, program verifying, erasing or erase verifying memory cells in the flash memory are typical operations that involve a number of logic tasks. The logic tasks can be performed in what is known by those skilled in the art as an embedded mode in the flash memory. In the embedded mode, the logic tasks associated with an operation are automated such that once the operation is initiated the logic tasks will be executed automatically in a synchronized fashion by the flash memory.
In addition to the embedded mode, the flash memory typically also includes a plurality of test modes where the read, program, program verify, erase and erase verify operations are performed during testing of the flash memory. Prior art systems and methods of performing an operation in the test modes involves manual application of externally supplied control signals to execute the logic tasks. Since the timing of some of the logic tasks is critical or must occur very quickly, known problems can occur unless the testing is done using expensive and sophisticated test equipment.
Prior art testing is very complex and requires that the test equipment is programmed to maintain the timing and synchronization of the logic tasks during the operations. The test equipment is also required to supply predetermined magnitudes of control signals to the flash memory. In addition, a change to the operations in the embedded mode of the flash memory typically requires changes to the programming and control voltages of the test equipment.
For the foregoing reasons, a need exists for memory devices that can perform operations in both the embedded mode and test modes without the use of expensive and sophisticated test equipment.
The present invention discloses a memory device that includes an embedded and test mode timer circuit to perform operations in both the embedded mode and a plurality of test modes. The preferred memory device is a flash memory and includes a state machine electrically connected with an embedded and test mode timer circuit. The embedded and test mode timer circuit and the state machine are also electrically connected with at least one logic circuit. As known in the art, the state machines are used to control the overall operation of the flash memory in response to instruction sets that are received by the state machine.
During an embedded mode in the preferred embodiment, the state machine receives instruction sets and activates the embedded and test mode timer circuit. As known in the art, the embedded mode is a mode that allows automated operation of the flash memory. The embedded and test mode timer circuit is activated to automatically direct the logic circuits to execute an operation such as a read, program, program verify, erase or erase verify based on a plurality of predetermined times. During a plurality of test modes, the state machine activates the embedded and test mode timer circuit to automatically direct a portion of the logic circuits at predetermined times and manually direct the remaining logic circuits.
The preferred embedded and test mode timer circuit includes a timer electrically connected with a plurality of decoders that are in turn electrically connected with at least one flip-flop. The flip-flops are electrically connected with the logic circuits. During the embedded mode, when the state machine receives instructions to perform an operation, the state machine activates the timer and a portion of the decoders. The portion of the decoders activated is a decoder group that is associated with, and controls, the operation to be performed. The timer generates and directs a plurality of predetermined times to the decoders. As the timer counts sequentially, the decoders in the decoder group monitor the timer and generate a plurality of control output signals that are directed to the flip-flops when a respective predetermined time is reached. The control output signal from each decoder in the decoder group activates the flip-flops to direct the logic circuits to perform a plurality of logic tasks to complete the operation.
When an operation such as a program, a program verify, an erase, an erase verify or a read is performed during a test mode, the state machine activates the embedded and test mode timer circuit to direct the logic circuits. The timer and the same decoder group that are associated with the operation in the embedded mode are activated. However, in the test mode, the timer and decoder group does not control all the logic circuits associated with the operation. The timer and the decoder group activate the flip-flops to direct a portion of the logic circuits and the remaining logic circuits are manually controlled. Effectively, the logic circuits for the test mode operation are split into three groups: 1) those logic circuits that are automatically directed to execute logic tasks at the beginning of the operation; 2) those logic circuits that are manually directed to execute logic tasks in the middle of the operation; and 3) those logic circuits that are automatically directed to execute logic tasks at the end of the operation. As would be recognized by those skilled in the art, the nature and number of logic tasks in each respective group are dependent on the particular operation within the test mode.
The state machine manually controls the logic circuits by activating the flip-flops within the embedded and test mode timer circuit to direct the logic circuits based on user control inputs to the flash memory. When the operation is initiated in the test mode, the logic circuits are directed by the timer, the decoder group and the flip-flops to automatically execute the logic tasks at the beginning of the operation based on the predetermined times generated by the timer. The logic circuits that include the logic tasks in the middle of the operation are no longer automated since the respective decoders are disabled and the operation is effectively suspended until they are completed manually. The user manually activates the flip-flops in the embedded and test mode timer circuit to direct the logic circuits to execute the logic tasks in the middle of the operation. Following completion of the logic tasks in the middle of the operation, the logic circuits are automatically directed to execute the logic tasks at the end of the operation by the timer, the decoder group and the flip-flops.
Those skilled in the art recognize that determining which logic tasks are placed in manual user control and which logic tasks remain automated by the timer as in the embedded mode is dependent on the operation being performed during the test mode. In addition, the decision of which logic tasks within a particular test mode operation are to be placed in manual control is dependent on what types of tests are to be performed.
Another preferred embodiment of the present invention, is a method of executing an operation in an embedded mode and in a plurality of test modes in a memory device that in the preferred embodiment is a flash memory. The operation is initiated with a state machine. The state machine then activates an embedded and test mode timer circuit to execute the operation. The embedded and test mode timer directs a plurality of logic circuits to complete the operation in both the embedded mode and the test modes in the same manner as in the previously set forth embodiments.
Presently known prior art memory timing architectures use timers for operations performed in the embedded mode and manually control operations in the test mode using expensive and sophisticated test equipment. The preferred embodiment of the present invention utilizes the timer and the same decoder group for an operation in either the embedded mode or the test mode. Since the test mode operation is performed using the embedded and test mode timer circuit and the state machine, the complexity of testing is greatly reduced thus avoiding the use of expensive and sophisticated test equipment.
In the preferred embodiment, the timing for the logic tasks where timing is critical, or must occur very quickly, is the same in both the embedded mode and during the test modes. Since the timing is the same, changes to the flash memory that affect the operation in the embedded mode also affect the operation in the test modes. In addition, since the critical timing is accomplished with the timer and decoders, manual direction of the logic circuits with the embedded and test mode timer circuit and the state machine can be accomplished with simple test equipment.